1. Field of the Invention
This invention relates to a semiconductor integrated circuit device having a plurality of flip-flops cascade-connected by having data output terminals respectively connected to data input terminals of the next-stage flip-flops and more particularly to a technique for resetting a plurality of flip-flops.
2. Description of the Related Art
Conventionally, in a semiconductor integrated circuit device having a plurality of flip-flops cascade-connected by having data output terminals respectively connected to data input terminals of the next-stage flip-flops, for example, the semiconductor integrated circuit device is configured as shown in FIG. 1 in order to simultaneously reset the flip-flops. A plurality of flip-flops 11-1, 11-2, . . . , 11-n are cascade-connected, that is, data output terminals Q thereof are sequentially and respectively connected to data input terminals D of the next-stage flip-flops. OR gates 12-1, 12-2, . . . are inserted in the signal transmission path of the flip-flops 11-1, 11-2, . . . , 11-n so that a reset signal RS can be input via the plurality of OR gates at the same time. That is, in the case of FIG. 1, circuits (OR gates 12-1, 12-2) which derive the logical OR of an original transfer signal (data) DA and a reset signal RS are respectively provided in the preceding stages of the first-stage flip-flop 11-1 and (n−1) th-stage flip-flop 11-(n−1). Then, when it becomes necessary to reset the flip-flops 11-1, 11-2, . . . , 11-n when the semiconductor integrated circuit device is powered ON, for example, a reset signal RS is supplied to the data input terminals D of the first-stage and (n−1)th-stage flip-flops 11-1, 11-(n−1) by inputting the reset signal RS to the OR gates 12-1, 12-2. After this, a normal clock signal CLK is input to the clock input terminals CK of the flip-flops 11-1, 11-2, . . . , 11-n to sequentially transfer the reset signal RS from the first-stage flip-flop 11-1 to the succeeding-stage flip-flops 11-2, 11-3, . . . .
Each of the OR gates 12-1, 12-2, . . . is provided for every preset number of flip-flops and all of the flip-flops 11-1, 11-2, . . . , 11-n can be reset in a short period of time by simultaneously inputting the reset signal RS via the OR gates 12-1, 12-2, . . . to start the reset operation.
However, with the above configuration, the circuits (OR gates 12-1, 12-2, . . . ) which derive the logical OR of the reset signal RS and the data DA are always present in the original signal transmission path. Therefore, when data DA is transferred, gate delay due to the presence of the OR gates 12-1, 12-2, . . . will occur. Further, wirings to transfer the reset signals RS are required in addition to the OR gates 12-1, 12-2, . . . . Therefore, the above configuration is disadvantageous from the viewpoint of the operation speed and pattern occupied area.
FIGS. 2A to 2E show examples of the conventional flip-flops with a reset function, for illustrating another conventional semiconductor integrated circuit device. FIG. 2A is a symbol diagram, FIG. 2B is a circuit diagram showing a concrete example of the configuration of a synchronous-reset-type flip-flop, FIG. 2C is a circuit diagram showing a concrete example of the configuration of an asynchronous-reset-type flip-flop, FIG. 2D is a circuit diagram showing an example of the configuration of a NOR gate used in each of the circuits shown in FIGS. 2B and 2C, and FIG. 2E is a timing chart showing the operation of each of the flip-flops shown in FIGS. 2B and 2C.
A flip-flop 13 with the reset function shown in FIG. 2A is configured as shown in FIG. 2B or 2C. The synchronous-reset-type flip-flop 13 shown in FIG. 2B includes a NOR gate 14, inverters 15, 16 and clocked inverters 17, 18, 19.
The asynchronous-reset-type flip-flop 13 shown in FIG. 2C includes clocked inverters 20 to 23 and NOR gates 24, 25.
As shown in FIG. 2D, each of the two-input NOR gates 14, 24 and 25 includes p-channel MOS transistors Tr1 to Tr3 and n-channel MOS transistors Tr4 to Tr6. In the NOR gate, a NOR signal indicating the logical NOR of two input signals A and B is output from a connection node O of the MOS transistors Tr3 and Tr4.
In the synchronous-reset-type flip-flop shown in FIG. 2B, the output terminal Q is set to a low level in synchronism with a rise edge (time t2) of the clock signal input to the clock input terminal CK when a reset signal input to the reset input terminal R is set to a high level. On the other hand, in the asynchronous-reset-type flip-flop shown in FIG. 2C, when a reset signal input to the reset input terminal R is set to a high level, the output terminal Q is set to a low level irrespective of the clock signal at this time point (time t1).
Like the circuit shown in FIG. 1, all of the flip-flops can be reset by using the above flip-flop with the reset function instead of each set of the OR gate 12-1, flop-flop 11-1 and the OR gate 12-2, flop-flop 11-(n−1) in the circuit shown in FIG. 1 or by providing the above flip-flop for every preset number of stages of a plurality of flip-flops which are cascade-connected to transfer a reset signal.
By using the flip-flops with the configurations shown in FIGS. 2A to 2D, gate delay becomes shorter in comparison with that occurring in the circuit in which the OR gates are additionally provided as shown in FIG. 1. However, at the starting time of the reset operation, since the logical levels of the input terminal and output terminal of each logical gate are indefinite, the probability that potentials of the input terminal and output terminal of each logical gate will transit becomes high and the power consumption becomes large.
As the prior art related to this invention, a shift register with a reset function in which the reset control operation can be easily performed without changing the number of constituents of a flip-flop is proposed in Jpn. Pat. Appln. KOKAI Publication No. 2000-187993. In the above prior art, four-series basic control signals are input to each flip-flop to simultaneously transmit an input signal to the last end of the flip-flops by switching the initialization control signal.